For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, leading to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Classical transistor scaling makes designing a transistor with higher drive current and/or lower leakage current increasingly difficult. Planar transistors suffer from the disadvantage of being difficult to build an asymmetric transistor in which engineering the source can be independent from engineering at the channel and drain ends of the transistor.